Thermal Characterization of Next-Generation Workloads on Heterogeneous MPSoCs

Next-generation High-Performance Computing (HPC) applications need to tackle outstanding computational complexity while meeting latency and Quality-of-Service constraints. Heterogeneous Multi-Processor Systems-on-Chip (MPSoCs), equipped with a mix of general-purpose cores and reconfigurable fabric for custom acceleration of computational blocks, are key in providing the flexibility to meet the requirements of next-generation HPC. However, heterogeneity brings new challenges to efficient chip thermal management. In this context, accurate and fast thermal simulators are becoming crucial to understand and exploit the trade-offs brought by heterogeneous MPSoCs. In this paper, we first thermally characterize a next-generation HPC workload, the online video transcoding application, using a highly-accurate Infra-Red (IR) microscope. Second, we extend the 3D-ICE thermal simulation tool with a new generic heat spreader model capable of accurately reproducing package surface temperature, with an average error of 6.8% for the hot spots of the chip. Our model is used to characterize the thermal behaviour of the online transcoding application when running on a heterogeneous MPSoC. Moreover, by using our detailed thermal system characterization we are able to explore different application mappings as well as the thermal limits of such heterogeneous platforms

Vitruvius+: An area-efficient RISC-V decoupled vector coprocessor for high performance computing applications

The maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of specialized hardware in processor cores for the High Performance Computing (HPC) application domain. In this article,1 we present Vitruvius+, the vector processing acceleration engine that represents the core of vector instruction execution in the HPC challenge that comes within the EuroHPC initiative. It implements the RISC-V vector extension (RVV) 0.7.1 and can be easily connected to a scalar core using the Open Vector Interface standard. Vitruvius+ natively supports long vectors: 256 double precision floating-point elements in a single vector register. It is composed of a set of identical vector pipelines (lanes), each containing a slice of the Vector Register File and functional units (one integer, one floating point). The vector instruction execution scheme is hybrid in-order/out-of-order and is supported by register renaming and arithmetic/memory instruction decoupling. On a stand-alone synthesis, Vitruvius+ reaches a maximum frequency of 1.4 GHz in typical conditions (TT/0.80V/25°C) using GlobalFoundries 22FDX FD-SOI. The silicon implementation has a total area of 1.3 mm2 and maximum estimated power of ~920 mW for one instance of Vitruvius+ equipped with eight vector lanes.This research has received funding from the European High Performance Computing Joint Undertaking (JU) under Framework Partnership Agreement No 800928 (European Processor Initiative) and Specific Grant Agreement No 101036168 (EPI SGA2). The JU receives support from the European Union’s Horizon 2020 research and innovation programme and from Croatia, France, Germany, Greece, Italy, Netherlands, Portugal, Spain, Sweden, and Switzerland. The EPI-SGA2 project, PCI2022-132935 is also co-funded by MCIN/AEI/10.13039/501100011033 and by the UE NextGen- erationEU/PRTR. This work has also been partially supported by the Spanish Ministry of Science and Innovation (PID2019-107255GB-C21/AEI/10.13039/501100011033).Peer ReviewedPostprint (author's final draft

Mechanisms of viral entry: sneaking in the front door

Recent developments in methods to study virus internalisation are providing clearer insights into mechanisms used by viruses to enter host cells. The use of dominant negative constructs, specific inhibitory drugs and RNAi to selectively prevent entry through particular pathways has provided evidence for the clathrin-mediated entry of hepatitis C virus (HCV) as well as the caveolar entry of Simian Virus 40. Moreover, the ability to image and track fluorescent-labelled virus particles in real-time has begun to challenge the classical plasma membrane entry mechanisms described for poliovirus and human immunodeficiency virus. This review will cover both well-documented entry mechanisms as well as more recent discoveries in the entry pathways of enveloped and non-enveloped viruses. This will include viruses which enter the cytosol directly at the plasma membrane and those which enter via endocytosis and traversal of internal membrane barrier(s). Recent developments in imaging and inhibition of entry pathways have provided insights into the ill-defined entry mechanism of HCV, bringing it to the forefront of viral entry research. Finally, as high-affinity receptors often define viral internalisation pathways, and tropism in vivo, host membrane proteins to which viral particles specifically bind will be discussed throughout

Thermal characterization of next-generation workloads on heterogeneous MPSoCs

Next-generation High-Performance Computing (HPC) applications need to tackle outstanding computational complexity while meeting latency and Quality-of-Service constraints. Heterogeneous Multi-Processor Systems-on-Chip (MPSoCs), equipped with a mix of general-purpose cores and reconfigurable fabric for custom acceleration of computational blocks, are key in providing the flexibility to meet the requirements of next-generation HPC. However, heterogeneity brings new challenges to efficient chip thermal management. In this context, accurate and fast thermal simulators are becoming crucial to understand and exploit the trade-offs brought by heterogeneous MPSoCs. In this paper, we first thermally characterize a next-generation HPC workload, the online video transcoding application, using a highly-accurate Infra-Red (IR) microscope. Second, we extend the 3D-ICE thermal simulation tool with a new generic heat spreader model capable of accurately reproducing package surface temperature, with an average error of 6.8% for the hot spots of the chip. Our model is used to characterize the thermal behaviour of the online transcoding application when running on a heterogeneous MPSoC. Moreover, by using our detailed thermal system characterization we are able to explore different application mappings as well as the thermal limits of such heterogeneous platforms

MANGO: Exploring Manycore Architectures for Next-GeneratiOn HPC Systems

The Horizon 2020 MANGO project aims at exploring deeply heterogeneous accelerators for use in High-Performance Computing systems running multiple applications with different Quality of Service (QoS) levels. The main goal of the project is to exploit customization to adapt computing resources to reach the desired QoS. For this purpose, it explores different but interrelated mechanisms across the architecture and system software. In particular, in this paper we focus on the runtime resource management, the thermal management, and support provided for parallel programming, as well as introducing three applications on which the project foreground will be validated

Accelerated surgery versus standard care in hip fracture (HIP ATTACK) : an international, randomised, controlled trial

Background: Observational studies have suggested that accelerated surgery is associated with improved outcomes in patients with a hip fracture. The HIP ATTACK trial assessed whether accelerated surgery could reduce mortality and major complications. Methods: HIP ATTACK was an international, randomised, controlled trial done at 69 hospitals in 17 countries. Patients with a hip fracture that required surgery and were aged 45 years or older were eligible. Research personnel randomly assigned patients (1:1) through a central computerised randomisation system using randomly varying block sizes to either accelerated surgery (goal of surgery within 6 h of diagnosis) or standard care. The coprimary outcomes were mortality and a composite of major complications (ie, mortality and non-fatal myocardial infarction, stroke, venous thromboembolism, sepsis, pneumonia, life-threatening bleeding, and major bleeding) at 90 days after randomisation. Patients, health-care providers, and study staff were aware of treatment assignment, but outcome adjudicators were masked to treatment allocation. Patients were analysed according to the intention-to-treat principle. This study is registered at ClinicalTrials.gov (NCT02027896). Findings: Between March 14, 2014, and May 24, 2019, 27 701 patients were screened, of whom 7780 were eligible. 2970 of these were enrolled and randomly assigned to receive accelerated surgery (n=1487) or standard care (n=1483). The median time from hip fracture diagnosis to surgery was 6 h (IQR 4\u20139) in the accelerated-surgery group and 24 h (10\u201342) in the standard-care group (p<0\ub70001). 140 (9%) patients assigned to accelerated surgery and 154 (10%) assigned to standard care died, with a hazard ratio (HR) of 0\ub791 (95% CI 0\ub772 to 1\ub714) and absolute risk reduction (ARR) of 1% ( 121 to 3; p=0\ub740). Major complications occurred in 321 (22%) patients assigned to accelerated surgery and 331 (22%) assigned to standard care, with an HR of 0\ub797 (0\ub783 to 1\ub713) and an ARR of 1% ( 122 to 4; p=0\ub771). Interpretation: Among patients with a hip fracture, accelerated surgery did not significantly lower the risk of mortality or a composite of major complications compared with standard care. Funding: Canadian Institutes of Health Research